发明名称 Low power latching circuits
摘要 <p>A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop.</p>
申请公布号 GB2519720(B) 申请公布日期 2015.09.09
申请号 GB20150003696 申请日期 2013.10.22
申请人 ARM LIMITED 发明人 VIRGILE JAVERLIAC;YANNICK MARC NEVERS;LAURENT CHRISTIAN SIBUET;SELMA LAABIDI
分类号 G11C11/412;G11C19/28;H03K3/037 主分类号 G11C11/412
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