| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a logical operation processing unit whose circuit size is small, capable of performing high-speed processing of multistage logical operation processing that is processed with a plurality of clocks.SOLUTION: Multiple cycle logical operation processing is executed with a logic circuit constituted of an input terminal I(0), an output terminal OUT, two sets of dynamic reconfigurable circuits C(0) 110, C(1) 120 to which a clock t is applied, two sets of storage element (register) groups R(0) 130, R(1) 140, and two sets of controllers 150, 160 for allocating reconfiguration circuits.</p> |
