发明名称 Multi-chip packaging structure and method
摘要 In one embodiment, a multi-chip packaging structure can include: (i) N chips, where N is an integer of at least two, and where an upper surface of each chip can include a plurality of pads; (ii) a lead frame with a chip carrier and a plurality of pins, where the N chips are stacked in layers on the chip carrier, and where a chip in an upper layer partially covers a chip in a lower layer such that the plurality of pads of the lower layer chip are exposed; (iii) a plurality of first bonding leads that can connect pads on one chip to pads on another chip; and (iv) a plurality of second bonding leads that can connect pads on at least one chip to the plurality of pins for external connection to the multi-chip packaging structure.
申请公布号 US9129947(B2) 申请公布日期 2015.09.08
申请号 US201313973132 申请日期 2013.08.22
申请人 Silergy Semiconductor Technology (Hangzhou) LTD 发明人 Tan Xiaochun;Chen Wei
分类号 H01L23/495;H01L23/00;H01L23/31 主分类号 H01L23/495
代理机构 代理人 Stephens, Jr. Michael C.
主权项 1. A multi-chip packaging structure, comprising: a) N chips, wherein N is an integer of at least two, and wherein an upper surface of each chip comprises a plurality of pads; b) a lead frame with a chip carrier and a plurality of pins, wherein said N chips are stacked in layers on said chip carrier, and wherein a first chip of said N chips situated in an upper layer comprises a control and driving circuit and partially covers a second chip of said N chips situated in a lower layer such that said plurality of pads of said second chip are exposed, and wherein said second chip comprises a power transistor; c) a plurality of first bonding leads configured to connect pads on said first chip to pads on said second chip, wherein a first of said plurality of pins is configured to withstand a high voltage, and wherein a second of said plurality of pins comprises a no connect pin; and d) a plurality of second bonding leads configured to connect pads on said first and second chips to said plurality of pins for external connection to said multi-chip packaging structure, wherein said first pin is directly connected to said chip carrier without connecting through any of said plurality of second bonding leads, and wherein said first and second pins are adjacent to each other.
地址 Hangzhou CN