发明名称 POP noise suppression circuit and system
摘要 A POP noise suppression circuit includes a power source terminal, a clock signal input terminal, a charge unit, a discharge unit, a common-mode voltage judging and switching control unit, a charge and discharge capacitor, and a ground terminal. The charge unit includes a first clock generation circuit for generating a first pair of non-overlapped clock signal, and a first equivalent resistor. The discharge unit includes a second clock generation circuit for generating a second pair of non overlapped clock signals, and a second equivalent resistor. The charge unit generates a charge voltage changing slowly to the charge and discharge capacitor. The discharge unit generates a discharge voltage changing slowly to the charge and discharge capacitor. A POP noise suppression system is further provided.
申请公布号 US9130516(B2) 申请公布日期 2015.09.08
申请号 US201213624825 申请日期 2012.09.21
申请人 IPGoal Microelectronics (Sichuan) Co., Ltd. 发明人 Yang Baoding
分类号 H03F1/30;H03G3/34 主分类号 H03F1/30
代理机构 代理人
主权项 1. A POP noise suppression circuit for an audio system, comprising: a power source terminal, a clock signal input terminal, a charge unit connected with said power source terminal and said clock signal input terminal, a discharge unit connected with said power source terminal, said clock signal input terminal and said charge unit, a common-mode voltage judging and switching control unit connected with said charge unit and said discharge unit, a charge and discharge capacitor connected with said charge unit, said discharge unit, and said common-mode voltage judging and switching control unit, and a ground terminal connected with said charge unit, said discharge unit, and said charge and discharge capacitor, wherein said charge unit comprises a first clock generation circuit connected with said clock signal input terminal and said common-mode voltage judging and switching control module for generating a first pair of non-overlapped clock signals, and a first equivalent resistor connected with said first clock generation circuit, said discharge unit comprises a second clock generation circuit connected with said clock signal input terminal and said common-mode voltage judging and switching control unit for generating a second pair of non overlapped clock signals, and a second equivalent resistor connected with said second clock generation circuit, said common-mode voltage judging and switching control module judges that whether a voltage of said charge and discharge capacitor reaches to a common-mode voltage, and switches working between said first clock generation circuit in said charge unit and said second clock generation circuit in said discharge unit, said charge unit generates a charge voltage changing slowly to said charge and discharge capacitor, said discharge unit generates a discharge voltage changing slowly to said charge and discharge capacitor.
地址 Chengdu, Sichuan Province CN