Hierarchical wafer yield prediction method and hierarchical lifetime prediction method

摘要

For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.

主权项

1. A method of a wafer fabrication process comprising:
performing the wafer fabrication process; measuring an overall die yield of a plurality of wafers from the wafer fabrication process; updating a profile of a yield prediction according to the overall die yield,
updating the profile of the yield prediction comprises:a processor determining a random yield and a systematic yield according to the overall die yield;the processor determining a systematic wafer acceptance test integral value and a systematic defect density integral value according to the systematic yield;the processor determining a wafer acceptance test coefficient according to the systematic wafer acceptance test integral value;the processor determining a metrology coefficient according to the wafer acceptance test coefficient;the processor determining a first systematic fault detection and classification value according to the metrology coefficient;the processor determining a second systematic fault detection and classification value according to the systematic defect density integral value;the processor determining a random defect density integral value according to the random yield;the processor determining a random fault detection and classification value according to the random defect density integral value; andthe processor generating an updated profile of the yield prediction according to the first systematic fault detection and classification value, the second systematic fault detection and classification value, and the random fault detection and classification value; and determining a yield of a subsequent wafer fabrication process using the updated profile of the yield prediction.