Word-line driver for memory

摘要

A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line.

主权项

1. A memory comprising:
a memory array having memory cells arranged in a plurality of rows wherein each of the rows is controlled by a corresponding word-line; and a plurality of word-line drivers, wherein each of the word-line drivers is configured to drive the corresponding word-line based at least on a first sub-group selection signal, a second sub-group selection signal, and group selection signals comprising a first group selection signal, a second group selection signal and a third group selection signal, and wherein each word-line driver comprises,
a first transistor having a gate terminal driven by the first group selection signal, a first conduction terminal driven by the second sub-group selection signal, and a second conduction terminal coupled to the corresponding word-line;a second transistor having a gate terminal driven by the second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the corresponding word-line; anda third transistor having a gate terminal driven by the third group selection signal, a first conduction terminal driven by the first sub-group selection signal, and a second conduction terminal coupled to the corresponding word-line, wherein the first group selection signal, the second group selection signal, the third group selection signal, the first sub-group selection signal, and the second sub-group selection signal are in a first operative configuration in a memory program/read operation, are in a second operative configuration in a memory erase operation, and are in a third operative configuration in a memory erase verify operation, wherein the word-line driver is configured to select the word-line for a memory program operation and a memory read operation when the second group selection signal and the second sub-group selection signal are at a first voltage, and the first group selection signal, the third group selection signal and the first sub-group selection signal are at a second voltage different than the first voltage, and wherein the word-line driver is configured to select the word-line for the memory erase operation when the first and third group selection signals and the first and second sub-group selection signals are at a negative voltage, and the second group selection signal is at a zero voltage.