发明名称 |
High speed signal generator |
摘要 |
A high-speed signal generator. A digital signal processing (DSP) block generates a set of N (where N is an integer and N≧2) parallel digital sub-band signals, each digital sub-band signal having frequency components within a spectral range between 0 Hz and ±Fs/2, where Fs is a sample rate of the digital sub-band signals. A respective Digital-to-Analog Converter (DAC) processes each digital sub-band signal to generate a corresponding analog sub-band signal, each DAC having a sample rate of Fs/2. A combiner combines the analog sub-band signals to generate an output analog signal having frequency components within a spectral range between 0 Hz and ±NFs/2. |
申请公布号 |
US9130678(B2) |
申请公布日期 |
2015.09.08 |
申请号 |
US201314102856 |
申请日期 |
2013.12.11 |
申请人 |
CIENA CORPORATION |
发明人 |
Krause David;Laperle Charles;Roberts Kim B. |
分类号 |
H04B10/61;H04J14/02;H04B10/516;H04B10/50;H04L27/26 |
主分类号 |
H04B10/61 |
代理机构 |
Daniels IP Services Ltd |
代理人 |
Daniels Kent;Daniels IP Services Ltd |
主权项 |
1. A high-speed signal generator comprising:
a digital signal processing (DSP) block configured to generate a set of N (where N is an integer and N≧2) parallel digital sub-band signals, each digital sub-band signal having frequency components within a spectral range between 0 Hz and ±Fs/2, where Fs is a sample rate of the digital sub-band signals; a respective Digital-to-Analog Converter (DAC) configured to process each digital sub-band signal to generate a corresponding analog sub-band signal, each DAC having a sample rate of Fs/2; and a combiner configured to combine the analog sub-band signals to generate an output analog signal having frequency components within a spectral range between 0 Hz and ±N·Fs/2, wherein the combiner is configured to combine the analog sub-band signals in the optical domain; wherein the digital signal processing (DSP) block comprises:
an encoding block configured to process an input digital signal to generate an encoded digital signal representative of the output analog signal;a Fast Fourier Transform (FFT) block configured to compute an array representative of a spectrum of the encoded digital signal;a Frequency Domain Processor (FDP) configured to process the array to generate a set of N sub-band arrays, each sub-band array including spectral components for a respective one of the parallel digital sub-band signals; anda respective Inverse Fast Fourier Transform (IFFT) block configured to process each sub-band array to generate a corresponding digital sub-band signal. |
地址 |
Hanover MD US |