Crystalline layer for passivation of III-N surface

摘要

Some embodiments of the present disclosure relates to a crystalline passivation layer for effectively passivating III-N surfaces. Surface passivation of HEMTs reduces or eliminates the surface effects that can otherwise degrade device performance. The crystalline passivation layer reduces the degrading effects of surface traps and provides a good interface between a III-nitride surface and an insulator (e.g., gate dielectric formed over the passivation layer).

主权项

1. A III-N (tri nitride) semiconductor device, comprising:
a buffer layer disposed above a semiconductor substrate; a crystalline or poly crystalline III-N layer disposed above the buffer layer; a crystalline passivation layer disposed above the crystalline or poly crystalline III-N layer; a source region and a drain region disposed onto and in direct contact with an upper region of the crystalline or poly crystalline III-N layer; a gate electrode disposed above the crystalline passivation layer at a lateral position between the source region and the drain region; a gate dielectric disposed beneath the gate electrode and abutting a top surface of the crystalline passivation layer, wherein the gate dielectric horizontally extends over upper surfaces of the source region and the drain region; and an amorphous passivation layer abutting the top surface of the crystalline passivation layer on opposite sides of the gate dielectric.