Transistor structures and integrated circuitry comprising an array of transistor structures

摘要

This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An electrically floating body region is disposed between the source/drain regions within the semiconductive material. A first gate spaced is apart from and capacitively coupled to the body region between the source/drain regions. A pair of opposing conductively interconnected second gates are spaced from and received laterally outward of the first gate. The second gates are spaced from and capacitively coupled to the body region laterally outward of the first gate and between the pair of source/drain regions. Methods of forming lines of capacitorless one transistor DRAM cells are disclosed.

主权项

1. A transistor structure, comprising:
a pair of spaced source/drain regions within semiconductive material; an electrically floating body region within the semiconductive material; the floating body region having a base, an insulative material being against the base, conductively doped semiconductive material being against the insulative material beneath the base; a first gate spaced apart from and capacitively coupled to the body region between the source/drain regions; and a pair of opposing conductively interconnected second gates spaced and electrically isolated from the first gate, the pair of second gates being laterally outward of the first gate, the second gates being spaced from and capacitively coupled to the body region laterally outward of the first gate and capacitively coupled to the body region between the pair of source/drain regions.