Virtual GPIO

摘要

A finite state machine is provided that both serializes virtual GPIO signals and deserializes virtual GPIO signals responsive to cycles of an external clock. The finite state machine frames the serialized virtual GPIO signals into frames each demarcated by a start bit and an end bit.

主权项

1. An integrated circuit, comprising:
a processor; a plurality of GPIO pins; a GPIO interface configured to receive a first set of GPIO signals from the processor and a second set of GPIO signals from the processor, wherein the GPIO interface is further configured to transmit the second set of GPIO signals to a remote processor over corresponding ones of the GPIO pins; a dedicated transmit pin; and a finite state machine (FSM) configured to receive the first set of GPIO signals from the GPIO interface and to serially transmit the first set of GPIO signals as a transmit set of virtual GPIO signals to the remote processor over the dedicated transmit pin responsive to cycles of an external clock.