Methods and systems for digital neural processing with discrete-level synapes and probabilistic STDP

摘要

Certain embodiments of the present disclosure support implementation of a digital neural processor with discrete-level synapses and probabilistic synapse weight training.

主权项

1. An electrical circuit, comprising:
a digital neural processing unit with one or more synapses and a post-synaptic neuron circuit connected to the synapses, wherein a weight of one of the synapses changes a value in discrete levels with a probability depending on a time elapsed between a pair of spikes originated from the post-synaptic neuron circuit and a pre-synaptic neuron circuit connected to the synapse.