| 摘要 |
In a liquid crystal display device having a configuration in which one pixel is divided into a plurality of sub-pixels to improve the view angle characteristic, the number of IC chips for driving a panel is reduced more than that in the conventional technique. A gate driver is provided with a first shift register (20A) corresponding to first gate bus lines (GLAi) (i=1 to n), a second shift register (20B) corresponding to second gate bus lines (GLBi), and AND operation circuits (ANDi) each outputting a signal indicating AND between an output signal (QAi) from the first shift register (20A) and an output signal (QBi) from the second shift register (20B). To the first gate bus line (GLAi), the output signal (QAi) from the first shift register (20A) is applied as it is as a scanning signal (GAi). To the second gate bus line (GLBi), an output signal from the AND operation circuit (ANDi) is applied as a scanning signal (GBi). |
| 主权项 |
1. A liquid crystal display device comprising:
a pixel portion which has a first sub-pixel portion including a first switching element, a first pixel electrode connected to a first conduction terminal of the first switching element, and a first pixel capacitance accumulating charges in accordance with potential of the first pixel electrode, and a second sub-pixel portion including a second switching element, a second pixel electrode connected to a first conduction terminal of the second switching element, and a second pixel capacitance accumulating charges in accordance with potential of the second pixel electrode, and forms a pixel matrix of n rows×m columns (n and m are natural numbers) in a display unit for displaying an image; a first scanning signal line provided in correspondence with each of the rows in the pixel matrix and connected to a control terminal of the first switching element; a second scanning signal line provided in correspondence with each of the rows of the pixel matrix and connected to a control terminal of the second switching element; a video signal line provided in correspondence with each of the columns of the pixel matrix and connected to a second conduction terminal of the first switching element and a second conduction terminal of the second switching element; a scanning signal line drive circuit for driving the first scanning signal line and the second scanning signal line; and a video signal line drive circuit for driving the video signal line, wherein the scanning signal line drive circuit includes:
a first shift register constructed by a plurality of first output signal generating stages corresponding to the first scanning signal line and outputting a first output signal sequentially becoming an on level stage by stage from the plurality of first output signal generating stages in accordance with a first clock signal group as two-phase clock signals which are deviated from each other by 180 degrees;a second shift register constructed by a plurality of second output signal generating stages corresponding to the second scanning signal line and outputting a second output signal sequentially becoming an on level stage by stage from the plurality of second output signal generating stages in accordance with a second clock signal group as two-phase clock signals which are deviated from each other by 180 degrees; andan AND operation unit performing an AND operation using the first output signal and the second output signal and outputting a third output signal indicative of an operation result, the display unit and the scanning signal line drive circuit are monolithically formed on a single substrate, and the first output signal is applied as a scanning signal to the first scanning signal line and the third output signal is applied as a scanning signal to the second scanning signal line, or the third output signal is applied as a scanning signal to the first scanning signal line and the second output signal is applied as a scanning signal to the second scanning signal line. |
