Self-biasing current reference

摘要

Current appearing on a bit-line with no memory cells asserted may be used during a bit-line pre-charge time before a read is performed so as to bias a gate-drain shorted PMOS pull-up device connected between the bit-line and a power supply at a VDD potential. The capacitance connected to the gate of this PMOS pull-up device may be used to “store” the resultant gate-source voltage when the drain is disconnected once the pre-charge time is completed. Once the read operation starts, the current of the PMOS pull-up device that has the “stored” resultant gate-source voltage is re-used as the reference for sensing the state of an asserted memory cell connected to the bit-line during the read operation thereof.

主权项

1. A method for determining a charge state of a memory cell having a floating gate, said method comprising the steps of:
sensing a first current in a hit-line when all memory cells coupled to the bit-line are de-asserted; converting the first current to a voltage; storing the voltage; providing a reference current based upon the stored voltage; comparing the reference current with a second current in the bit-lime when a single memory cell. connected to the bit-fine is asserted during a read operation thereof; and determining a bit value charge state stored in the single memory cell from the comparison of the reference current with the second current.