发明名称 |
Self-biasing multi-reference |
摘要 |
Current appearing on a bit-line with no memory cells asserted may be used during a bit-line pre-charge time before a read is performed so as to bias a gate-drain shorted PMOS pull-up device connected between the bit-line and a power supply at a VDD potential. The capacitance connected to the gate of this PMOS pull-up device may be used to “store” the resultant gate-source voltage when the drain is disconnected once the pre-charge time is completed. Once the read operation starts, the current of the PMOS pull-up device that has the “stored” resultant gate-source voltage and the “stored” resultant gate-source voltage itself are re-used as the references, or multi-reference, for sensing the state of an asserted memory cell connected to the bit-line during the read operation thereof. |
申请公布号 |
US9129680(B2) |
申请公布日期 |
2015.09.08 |
申请号 |
US201314029616 |
申请日期 |
2013.09.17 |
申请人 |
MICROCHIP TECHNOLOGY INCORPORATED |
发明人 |
Mietus David Francis |
分类号 |
G11C7/06;G11C16/06;G11C7/14;G11C16/24;G11C16/28;G11C13/00 |
主分类号 |
G11C7/06 |
代理机构 |
Slayden Grubert Beard PLLC |
代理人 |
Slayden Grubert Beard PLLC |
主权项 |
1. A method for determining a charge state of a memory cell having a floating gate, said method comprising the steps of:
sensing a first current in a bit-line when all memory cells coupled to the bit-line are de-asserted; converting the first current to a voltage; storing the voltage; providing a reference current based upon the stored voltage; providing a voltage reference used as an input for a sense amplifier from the stored voltage; comparing the reference current to a second current in the bit-line with the sense amplifier when a single memory cell connected to the bit-line is asserted during a read operation thereof; and determining from the sense amplifier output a bit value charge state stored in the single memory cell from the comparison of the reference current with the second current. |
地址 |
Chandler AZ US |