| 发明名称 | Memory device | ||
| 摘要 | Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections. | ||
| 申请公布号 | US9129861(B2) | 申请公布日期 | 2015.09.08 |
| 申请号 | US201414530638 | 申请日期 | 2014.10.31 |
| 申请人 | SAMSUNG ELECTRONICS CO., LTD. | 发明人 | Seol Kwang Soo;Kang JinTae;Cho Seong Soon |
| 分类号 | G11C11/34;G11C16/04;H01L27/115;H01L29/792;H01L29/423;H01L29/66;H01L29/788;H01L29/06;H01L29/41 | 主分类号 | G11C11/34 |
| 代理机构 | Renaissance IP Law Group LLP | 代理人 | Renaissance IP Law Group LLP |
| 主权项 | 1. A memory device, comprising: first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction; multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines, wherein the sets are sequentially arranged in the second direction; a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line; a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line; and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections. | ||
| 地址 | KR | ||