| 发明名称 |
CHIP PACKAGE STRUCTURE |
| 摘要 |
In one embodiment, a chip package structure can include: (i) a substrate; (ii) a top chip including a plurality of vias arranged through the top chip to form electrical connections between an active surface of the top chip and a back surface of the top chip; (iii) a redistribution layer arranged on the back surface of the top chip; and (iv) a plurality of wire bonds that form electrical connections between the substrate and electrodes on the redistribution layer on the back surface of the top chip. |
| 申请公布号 |
US2015249068(A1) |
申请公布日期 |
2015.09.03 |
| 申请号 |
US201514613593 |
申请日期 |
2015.02.04 |
| 申请人 |
Silergy Semiconductor Technology (Hangzhou) LTD |
发明人 |
Ye Jiaming |
| 分类号 |
H01L25/065;H01L23/48;H01L23/00 |
主分类号 |
H01L25/065 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A chip package structure, comprising:
a) a substrate; b) a top chip comprising a plurality of vias arranged through said top chip to form electrical connections between an active surface of said top chip and a back surface of said top chip; c) a redistribution layer arranged on said back surface of said top chip; and d) a plurality of wire bonds that form electrical connections between said substrate and electrodes on said redistribution layer on said back surface of said top chip. |
| 地址 |
Hangzhou CN |
