发明名称 |
Method To Form Group III-V And Si/Ge FINFET On Insulator And Integrated Circuit Fabricated Using The Method |
摘要 |
A method includes providing a structure having a substrate, a first electrically insulating layer overlying the substrate, a first semiconductor layer comprised of a first semiconductor material overlying the first electrically insulating layer, a second electrically insulating layer overlying the first semiconductor layer in a first portion of the structure and a second semiconductor layer comprised of a second, different semiconductor material overlying the second electrically insulating layer in the first portion. The method further includes growing additional first semiconductor material on the first semiconductor layer in a second portion of the structure to form a regrown semiconductor layer; forming fins; forming gate structures orthogonal to the fins and removing at least a portion of the first semiconductor layer in the first portion of the structure to form a void and filling the void with insulating material. Structures formed by the method are also disclosed. |
申请公布号 |
US2015249100(A1) |
申请公布日期 |
2015.09.03 |
申请号 |
US201514711019 |
申请日期 |
2015.05.13 |
申请人 |
International business Machines Corporation |
发明人 |
Czornomaz Lukas;Fompeyrine Jean;Leobandung Effendi |
分类号 |
H01L27/12;H01L29/161;H01L29/20;H01L27/092 |
主分类号 |
H01L27/12 |
代理机构 |
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代理人 |
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主权项 |
1. A structure, comprising:
a substrate, a first electrically insulating layer overlying a surface of the substrate, a first semiconductor layer comprised of a first semiconductor material overlying the first electrically insulating layer, a second electrically insulating layer overlying the first semiconductor layer in a first portion of the structure, and a second semiconductor layer comprised of a second semiconductor material different from the first semiconductor material overlying the second electrically insulating layer in the first portion; additional first semiconductor material on the first semiconductor layer in a second portion of the structure; a plurality of substantially parallel fins formed in the additional first semiconductor layer and in the second semiconductor layer; a plurality of substantially parallel gate structures disposed orthogonal to the plurality of fins; and a void disposed in the first portion of the structure between the first electrically insulating layer and the second electrically insulating layer. |
地址 |
Armonk NY US |