CACHE MEMORY CONTROL CIRCUIT AND PROCESSOR

摘要

According to an embodiment, a cache memory control circuit includes: a hit determination section; a refill processing section; a search section configured to determine a refill candidate way by searching for the way candidate for a refill process from a plurality of ways based on an LRU algorithm when the hit determination section detects a cache miss; a binary tree information section configured to store binary tree information for the LRU algorithm; a conflict detection section; and a control section. The control section updates the binary tree information in the binary tree information section by using way information of the way where the refill process is being executed when the conflict detection section determines that the way where the refill process is being executed and the refill candidate way match each other.

主权项

1. A cache memory control circuit configured to control a cache memory having a plurality of ways and storing cache data, the cache memory control circuit comprising:
a cache miss detection section configured to detect a cache miss for an access request; a refill processing section configured to refill the cache memory by replacing the cache data; a search section configured to determine a refill candidate way by searching the plurality of ways based on a predetermined algorithm when the cache miss is detected; an information storage section configured to store predetermined information for the predetermined algorithm; a match determination section configured to determine whether or not a way being refilled for a first cache miss and the refill candidate way for a second cache miss detected after the first cache miss match each other; and a control section configured to update the predetermined information by using information of the way being refilled when the way being refilled and the refill candidate way are determined to match each other.