HIGH PERFORMANCE STANDARD CELL

摘要

A transistor cell is provided that includes a dummy gate overlaying a continuous oxide definition (OD) region. A first portion of the OD region adjacent a first side of the dummy forms the drain. The cell includes a local interconnect structure that couples the dummy gate and a portion of the OD region adjacent a second opposing side of the dummy gate to a source voltage.

主权项

1. A cell comprising:
a continuous oxide definition (OD) region defined in a substrate; a gate for a transistor between a first dummy gate and a second dummy gate, wherein a source for the transistor is defined in a first portion of the OD region between the gate and the first dummy gate, and wherein a drain for the transistor is defined in a second portion of the OD region between the gate and a first side of the second dummy gate; a first gate-directed local interconnect coupled to a third portion of the OD region adjacent a second opposing side of the second dummy gate; and a first diffusion-directed local interconnect configured to couple the first gate-directed local interconnect to the second dummy gate.