METHODS OF FORMING DIFFERENT SPACER STRUCTURES ON INTEGRATED CIRCUIT PRODUCTS HAVING DIFFERING GATE PITCH DIMENSIONS AND THE RESULTING PRODUCTS

摘要

One example disclosed herein involves forming source/drain conductive contacts to first and second source/drain regions, the first source/drain region being positioned between a first pair of transistor devices having a first gate pitch dimension, the second source/drain region being positioned between a second pair of transistor devices having a second gate pitch dimension that is greater than the first gate pitch dimension, wherein the first and second pairs of transistor devices have a gate structure and sidewall spacers positioned adjacent the gate structure.

主权项

1. A method of forming source/drain conductive contacts to first and second source/drain regions, said first source/drain region being positioned between a first pair of transistor devices having a first gate pitch dimension, said second source/drain region being positioned between a second pair of transistor devices having a second gate pitch dimension that is greater than said first gate pitch dimension, wherein said first and second pairs of transistor devices have a gate structure and sidewall spacers positioned adjacent the gate structure, the method comprising:
forming a first layer of insulating material above said first and second source/drain regions; forming a second layer of insulating material above said first layer of insulating material; forming first and second contact openings above said first and second source/drain regions, wherein forming said first contact opening removes substantially all of said first layer of insulating material positioned above said first source/drain region and between facing sidewall spacers on said first pair of transistor devices having said first gate pitch, and wherein forming said second contact opening removes some, but not all, of said first layer of insulating material positioned above said second source/drain region and between facing sidewall spacers on said second pair of transistor devices having said second gate pitch, said second contact opening extending through a portion of said first layer of insulating material; performing an etching process through said first contact opening to remove the facing sidewall spacers on said first pair of transistor devices and thereby expose facing edges of the gate structures on said first pair of transistor devices; performing a common deposition and etch process sequence to form first and second low-k sidewall spacers within said first and second contact openings, respectively, wherein said first low-k sidewall spacer contacts the exposed facing edges of the gate structure of said first pair of transistor devices and said second low-k sidewall spacer is formed on said first layer of insulating material within said second contact opening; and forming source/drain conductive contacts in said first and second contact openings.