Semiconductor Device, Method for Driving the Same, and Electronic Appliance

摘要

A semiconductor device that suppresses operation delay due to stop and restart of the supply of a power supply potential is provided. A potential corresponding to data held while power supply potential is continuously supplied is backed up in a node connected to a capacitor while the supply of the power supply potential is stopped. Then, by utilizing change in resistance of a channel in a transistor whose gate is the node, the data is restored with restart of the supply of the power supply potential. Note that by supplying a high potential to the node before the data back up, high-speed and accurate data back up is possible.

主权项

1. A semiconductor device comprising:
a first circuit comprising a first node and a second node; a second circuit comprising first to sixth transistors, a third node, a fourth node, and a first wiring; and a third circuit comprising seventh to ninth transistors, first to N-th (N is an even number of 2 or more) inverter circuits, and a second wiring, wherein the first node is configured to hold one of a first potential and a second potential, wherein the second node is configured to hold the other of the first potential and the second potential, wherein the first node is electrically connected to the third node via the first transistor, and is electrically connected to the first wiring via the fifth and sixth transistors, wherein the second node is electrically connected to the fourth node via the fourth transistor, and is electrically connected to the first wiring via the second and third transistors, wherein a gate of the second transistor is electrically connected to the third node, wherein a gate of the fifth transistor is electrically connected to the fourth node, wherein one of a source and a drain of the seventh transistor is electrically connected to the third node, wherein one of a source and a drain of the eighth transistor is electrically connected to the fourth node, wherein the other of the source and the drain of the seventh transistor and the other of the source and the drain of the eighth transistor are electrically connected to the second wiring via the first to N-th inverter circuits, wherein a gate of the seventh transistor and a gate of the eighth transistor are electrically connected to the second wiring via the ninth transistor, and wherein the first, fourth, seventh, and eighth transistors each comprise an oxide semiconductor in a channel formation region.