PACKET OUTPUT PROCESSING

摘要

A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE determines an order in which to transmit the packet among a number of packets, where the PSE determines the order based on information indicated in the metapacket. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.

主权项

1. A circuit for managing transmittal of packets, the circuit comprising:
a packet descriptor manager (PDM) configured to generate a metapacket and a descriptor from a command signal, the command signal identifying a packet to be transmitted by the circuit; a packet scheduling engine (PSE) configured to determine an order in which to transmit the packet among a plurality of packets, the PSE determining the order based on a size and a destination of the packet indicated in the metapacket; and a packet engines and buffering module (PEB) module configured to perform processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor, the PEB causing the processed packet to be transmitted toward the destination.