Methods and Apparatus for SRAM Cell Structure

摘要

An SRAM cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second CVdd node, a first and a second CVss node, at a bit line node, at a bit line bar node, at a data node and at a data bar node; and second level contacts formed on each of the first level contacts at the first and second CVdd nodes, the first and second CVss nodes, the bit line node and the bit line bar node; wherein the first level contacts formed at the data node and the data bar node do not have a second level contact formed thereon. In another embodiment, a word line is formed and bit lines and a CVdd and a CVss line are formed overlying the SRAM cell and coupled to the corresponding ones of the nodes. Methods are disclosed for forming the cell structure.

主权项

1. A method, comprising:
receiving an SRAM circuit design for forming an array of SRAM cells on a semiconductor substrate; determining whether a double level photolithography process is to be used for second level contacts in the SRAM cells; based on the determining, selecting a cell layout including a double level patterning process for second level contacts or selecting a cell layout with a single level patterning process for second level contacts for the SRAM cells; and using the layout selected, forming the array of SRAM cells on the semiconductor substrate.