发明名称 |
COMPONENT PLACEMENT WITH REPACKING FOR PROGRAMMABLE LOGIC DEVICES |
摘要 |
Systems and methods are disclosed herein to provide improved placement of components in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The method also includes determining a layout comprising positions of components of the PLD configured to perform the operations. The method also includes performing a timing analysis on the layout. The method also includes selectively adjusting the positions of the components using the timing analysis. Related systems and non-transitory machine-readable mediums are also provided. |
申请公布号 |
US2015248512(A1) |
申请公布日期 |
2015.09.03 |
申请号 |
US201414194484 |
申请日期 |
2014.02.28 |
申请人 |
Lattice Semiconductor Corporation |
发明人 |
Shen Yinan;Zhao Jun |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
1. A computer-implemented method comprising:
receiving a design identifying operations to be performed by a programmable logic device (PLD); determining a layout comprising positions of components of the PLD configured to perform the operations; performing a timing analysis on the layout; and selectively adjusting the positions of the components using the timing analysis. |
地址 |
Hillsboro OR US |