| 发明名称 |
CALCULATING CIRCUIT-LEVEL LEAKAGE USING THREE DIMENSIONAL TECHNOLOGY COMPUTER AIDED DESIGN AND A REDUCED NUMBER OF TRANSISTORS |
| 摘要 |
A method for calculating leakage of a circuit including a plurality of transistors includes simulating a three-dimensional model of the circuit, wherein the simulating accounts for a subset of the plurality of the transistors that includes less than all of the plurality of transistors, and calculating the leakage in accordance with the three-dimensional model. |
| 申请公布号 |
US2015247890(A1) |
申请公布日期 |
2015.09.03 |
| 申请号 |
US201414194225 |
申请日期 |
2014.02.28 |
| 申请人 |
International Business Machines Corporation |
发明人 |
JOSHI RAJIV V.;Kim Keunwoo |
| 分类号 |
G01R31/02;G01R31/12 |
主分类号 |
G01R31/02 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method for calculating leakage of a circuit comprising a plurality of transistors, the method comprising:
simulating a three-dimensional model of the circuit, wherein the simulating accounts for a subset of the plurality of the transistors that includes less than all of the plurality of transistors; and calculating the leakage in accordance with the three-dimensional model. |
| 地址 |
Armonk NY US |
