BIAS CIRCUITS AND METHODS FOR STACKED DEVICES

摘要

Embodiments of the present disclosure include a bias circuit (101) for generating bias voltages to stacked transistors (M2-MN). In one embodiment, stacked transistors (M2-MN) are coupled between an input transistor (Ml) and an output node. A modulated power supply voltage (Vdd(t)) and an input signal (Vin) produce a voltage (Vo) at the output node. The modulated power supply voltage (Vdd(t)) is provided as an input to the bias circuit (101). Bias voltages are generated that change with the power supply voltage (Vdd(t)). In one embodiment, particular transistors in the stack are biased so that their source and drain terminals are effectively short circuited when the power supply voltage (Vdd(t)) is reduced.