发明名称 |
Time-to-Digital Converter and Related Method |
摘要 |
A device includes a delay line, a first readout circuit electrically connected to the delay line, a second readout circuit electrically connected to the delay line, and a phase interpolator electrically connected to the second readout circuit. |
申请公布号 |
US2015248114(A1) |
申请公布日期 |
2015.09.03 |
申请号 |
US201514714000 |
申请日期 |
2015.05.15 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Chien Jinn-Yeh |
分类号 |
G04F10/00 |
主分类号 |
G04F10/00 |
代理机构 |
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代理人 |
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主权项 |
1. A method comprising:
receiving a signal by a delay line; receiving a first clock signal and phase interpolating therefrom a second clock signal; selecting the first clock signal or the second clock signal in response to a control signal and outputting the selected first clock signal or second clock signal to a readout circuit; and receiving output signals from the delay line using the readout circuit while clocking the readout circuit at the selected first clock signal or second clock signal. |
地址 |
Hsin-Chu TW |