发明名称 半導体装置、情報処理装置およびエラー検出方法
摘要 <p>Each of (n−1) 2-bit checking units, where n is an integer larger than or equal to 4, receives n-bit redundant encoded data generated from 1-bit input data, and outputs 2-bit check data based on a result of comparison between bits of the encoded data, combinations of the bits differing in each comparison. An all-bit checking unit outputs all-bit check data based on exclusive ORs of all-bit of the encoded data. An error detecting unit detects errors in the encoded data on the basis of the (n−1) sets of 2-bit check data and the all-bit check data, and outputs the input data on the basis of the result of error detection.</p>
申请公布号 JP5772192(B2) 申请公布日期 2015.09.02
申请号 JP20110101887 申请日期 2011.04.28
申请人 发明人
分类号 H03M13/03;G06F12/16;G11C29/42 主分类号 H03M13/03
代理机构 代理人
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