发明名称 AN ACCELERATION SYSTEM IN 3D DIE-STACKED DRAM
摘要 A memory device can include: a logic layer which realizes at least one among a peripheral, an interface, and a BIST module and includes a reconfigurable accelerator (RA), wherein the reconfigurable accelerator is located in a vacant space of the logic layer and processes a part of work which the memory device processes; and at least one data layer storing data.
申请公布号 KR20150100042(A) 申请公布日期 2015.09.02
申请号 KR20140021342 申请日期 2014.02.24
申请人 ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE;UNIST ACADEMY-INDUSTRY RESEARCH CORPORATION 发明人 KIM, YONG JOO;LEE, JIN YONG;PAEK, YUN HEUNG;LEE, JONG EUN
分类号 G06F12/00;G06F13/14;G11C5/02 主分类号 G06F12/00
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