Complementary metal-oxide-semiconductor device comprising silicon and germanium and method for manufacturing thereof

摘要

Disclosed are complementary metal-oxide-semiconductor (CMOS) devices and methods of manufacturing such CMOS devices. In some embodiments, an example CMOS device may include a substrate, and a buffer layer formed on the substrate, where the buffer layer comprises Si1-xGex, where x is less than 0.5. The example CMOS device may further include one or more pMOS channel layer elements, where each pMOS channel layer element comprises Si1-yGey, and where y is greater than x. The example CMOS device may still further include one or more nMOS channel layer elements, where each nMOS channel layer element comprises Si1-zGez, and where z is less than x. In some embodiments, the example CMOS device may be a fin field-effect transistor (FinFET) CMOS device and may further include a first fin structure including the pMOS channel layer element(s) and a second fin structure including the nMOS channel layer element(s).

主权项

1. A fin field-effect transistor (FinFET) complementary metal-oxide-semiconductor (CMOS) device, comprising:
a substrate; a buffer layer formed on the substrate, wherein the buffer layer comprises Si1-xGex, wherein x is greater than 0 and less than 0.5; one or more pMOS channel layer elements formed on the buffer layer, wherein each pMOS channel layer element comprises Si1-yGey, wherein y is greater than x; one or more nMOS channel layer elements formed on the buffer layer, wherein each nMOS channel layer element comprises Si1-zGez, wherein z is less than x; a first fin structure comprising the one or more pMOS channel layer elements; a second fin structure comprising the one or more nMOS channel layer elements; and further comprising at least one of:
(i) a first elevated source-drain (E S/D) electrode formed adjacent to the one or more pMOS channel layer elements, wherein the first E S/D comprises Si1-pGep, and wherein p is greater than x, and a second E S/D formed adjacent to the one or more pMOS channel layer elements, wherein the second E S/D comprises Si1-kGek, and wherein k is greater than p; or(ii) a third elevated source-drain (E S/D) electrode formed adjacent to the one or more nMOS channel layer elements, wherein the first E S/D comprises Si1-ppGepp, and wherein pp is less than x, and a fourth E S/D formed adjacent to the one or more nMOS channel layer elements, wherein the second E S/D comprises Si1-kkGekk, and wherein kk is less than pp.