Single photon counting detector system having improved counter architecture

摘要

A single photon counting detector system has a layer of photosensitive material and an N×M array of photo-detector diodes. Each photo-detector diode has a bias potential interface and a diode output interface. The bias potential interface is connected to bias potential. An N×M array of high gain, low noise readout unit cells is provided, one readout unit cell for each photo-detector diode. Each readout unit cell has an input interface connected to the diode output interface, a high-gain voltage amplifier with an integration capacitor at least two parallel lines of digital counters, each having a comparator with an individually selectable threshold and a gateable section to determine the counting intervals of the digital counters. A multiplexer allows access to the readout cell unit either on a per pixel basis or for several pixels in parallel to read out the digital counter to a data processor transferring the data off chip.

主权项

1. A single photon counting detector system, comprising:
a) a layer of photosensitive material; b) an N×M array of photo-detector diodes arranged in said layer of photosensitive material, each of said photo-detector diodes having a bias potential interface and a diode output interface, said bias potential interface of each of each of said photo-detector diode being connected to a bias potential; c) an N×M array of high gain, low noise readout unit cells, one of said readout unit cells for each one of said photo-detector diodes; d) each readout unit cell having:
d1) an input interface connected to said diode output interface, a high-gain voltage amplifier with an integration capacitor, said high-gain voltage amplifier connected to said input interface;d2) at least two parallel lines of digital counters;d3) each of said lines including a comparator connected to obtain an output signal from said high-gain voltage amplifier, said comparator having an individually selectable threshold, each of said lines including a gateable section for determining a counting interval of said digital counters individually for each line of digital counters, said gateable section configured for gating a fixed frequency signal with an output of said comparator; and e) a multiplexer device connected to said digital counters to allow access to said readout cell unit either on a per pixel basis or for a plurality of pixels in parallel to read out data from said digital counters to a data processor.