Tap linking module test access port controller with enable input

摘要

An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.

主权项

1. A test access port formed in an integrated circuit on a substrate, comprising:
A. a test access port controller having a test mode select input, a test clock input, an enable input, and control outputs; B. a multiplexer having a test data output, a first input, and a second input; C. data registers having control inputs connected to the control outputs of the controller, a test data input and a test data output, the test data output being connected to the first input of the multiplexer; D. an instruction register having control inputs connected to the control outputs of the test access port controller, a test data input and a test data output, the instruction register being connected between the second input of the multiplexer and the test data input of the data registers, the instruction register having a select output; E. a scan cell separate from the instruction register connected in series with the instruction register coupled to the second input of the multiplexer and the test data input of the data registers, the scan cell having a control input connected to the control inputs of the instruction register, and an address output; and F. a demultiplexer having an input connected to the select output of the instruction register, a control input connected to the address output of the scan cell, a select output and a select one output.