Thin film transistor array panel and manufacturing method thereof

摘要

Instead of forming contact holes the same way in both the non-image forming peripheral area (PA) and the image forming display area of a thin film transistor array panel, contact holes in the DA are formed to be substantially smaller than those in the PA for thereby improving an aperture ratio of the corresponding display device. In an exemplary embodiment, an inorganic gate insulating layer is not etched in the DA and only an inorganic first passivation layer among inorganic insulating layers positioned in the DA is etched to allow communication between the drain electrode and the corresponding field generating electrode. On the other hand, in the peripheral area, plural inorganic insulating layers such as the gate insulating layer, the first passivation layer, and the second passivation layer positioned on the gate wire and the data wire are simultaneously etched to form second contact holes and third contact holes exposing respective gate pads and data pads.

主权项

1. A thin film transistor array panel for use in a display device and comprising:
a substrate having a display area through which image forming light rays of the display device will pass and a peripheral area disposed near the display area and through which image forming light rays of the display device will not pass; a gate line positioned in the display area of the substrate; a gate pad connected to the gate line and positioned in the peripheral area of the substrate; a gate insulating layer positioned on the gate line and the gate pad; a data line and a drain electrode positioned in the display area of the substrate; a data pad connected to the data line and positioned in the peripheral area of the substrate and on the gate insulating layer; a first passivation layer having a first contact hole defined therethrough for exposing a portion of the drain electrode; a first field generating electrode connected to the drain electrode through the first contact hole of the first passivation layer; a second passivation layer positioned on the first field generating electrode; and a second field generating electrode positioned on the second passivation layer, wherein the first field generating electrode include a portion positioned in the first contact hole covered by the second passivation layer, wherein the gate insulating layer, the first passivation layer, and the second passivation layer have second contact hole extending therethrough and positioned in the peripheral area for exposing the gate pad, and wherein the first passivation layer and the second passivation layer have a third contact hole extending therethrough and positioned in the peripheral area for exposing the data pad.