Synchronizing a translation lookaside buffer with an extended paging table

摘要

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

主权项

1. A processor comprising:
decode logic to decode an instruction providing an address space context corresponding to a page table for a guest address space of a virtualization based system; and execution logic, responsive to the decoded instruction, to invalidate a corresponding Translation Lookaside Buffer (TLB) entry with a mapping from the page table of the virtualization based system.