Methods for controlling microloading variation in semiconductor wafer layout and fabrication

摘要

Problematic open areas are identified in a semiconductor wafer layout. The problematic open areas have a size variation relative to one or more neighboring open areas of the layout sufficient to cause adverse microloading variation. In one embodiment, the adverse microloading variation is controlled by shifting a number of layout features to interdict the problematic open areas. In another embodiment, the adverse microloading variation is controlled by defining and placing a number of dummy layout features to shield actual layout features that neighbor the problematic open areas. In another embodiment, the adverse microloading variation is controlled by utilizing sacrificial layout features which are actually fabricated on the wafer temporarily to eliminate microloading variation, and which are subsequently removed from the wafer to leave behind the desired permanent structures.

主权项

1. A method for controlling microloading variation in a semiconductor wafer layout, comprising:
identifying, by using a computer, a first open area in a layout having a size variation relative to one or more neighboring open areas of the layout sufficient to cause adverse microloading variation, the first open area located between layout features of a first set of linear-shaped conductive structures and layout features of a second set of linear-shaped conductive structures, each layout feature of the first and second sets of linear-shaped conductive structures oriented to extend lengthwise in a first direction, end-by-end positioned layout features of the first set of linear-shaped conductive structures separated by a first distance as measured in the first direction, side-by-side positioned layout features of the first set of linear-shaped conductive structures separated by a second distance as measured in a second direction perpendicular to the first direction; and defining and placing dummy layout features, by using the computer, within the first open area so as to shield layout features of the first set of linear-shaped conductive structures from adverse microloading variation, wherein each dummy layout feature is defined to form a corresponding physical structure having a linear-shape extending lengthwise in the first direction, and wherein each physical structure corresponding to a given dummy layout feature is not connected within an electrical circuit, and wherein each dummy layout feature that is positioned end-by-end with a given layout feature of any of the first set of linear-shaped conductive structures is separated from the given layout feature by the first distance as measured in the first direction, and wherein each dummy layout feature that is positioned side-by-side with a given layout feature of any of the first set of linear-shaped conductive structures is separated from the given layout feature by the second distance as measured in the second direction, wherein the dummy layout features are defined and placed around the first open area on each of four perpendicularly related sides of the first open area to provide for shielding of the layout features of the first set of linear-shaped conductive structures neighboring the first open area, wherein multiple dummy layout features are placed along each of the four perpendicularly related sides of the first open area; and recording the layout in a digital format on a computer readable medium for fabrication.