Pseudo cache memory in a multi-core processor (MCP)

摘要

Specifically, under the present invention, a cache memory unit can be designated as a pseudo cache memory unit for another cache memory unit within a common hierarchal level. For example, in case of cache miss at cache memory unit “X” on cache level L2 of a hierarchy, a request is sent to a cache memory unit on cache level L3 (external), as well as one or more other cache memory units on cache level L2. The L2 level cache memory units return search results as a hit or a miss. They typically do not search L3 nor write back with the L3 result even (e.g., if it the result is a miss). To this extent, only the immediate origin of the request is written back with L3 results, if all L2s miss. As such, the other L2 level cache memory units serve the original L2 cache memory unit as pseudo caches.

主权项

1. A pseudo memory system, comprising:
a first memory unit mounted on a bus; a first manager coupled to an input and an output of the first memory unit; and a second memory unit mounted on the bus, the second memory unit being on a common hierarchical level with the first memory unit and the first cache manager being configured to:
designate a the memory block of the second memory unit as a pseudo memory unit for the first memory unit,receive a request, and send the request simultaneously to a third memory unit located externally on a higher hierarchical level than the common hierarchical level and to the memory block of the second memory unit, andenable the second memory unit to function as a next-level higher cache to the first memory unit following a cache memory miss on the common hierarchical level.