发明名称 Accurate and cost efficient linear hall sensor with digital output
摘要 One embodiment of the present invention relates to a magnetic sensor circuit having a magnetic field sensor device configured to generate a digital signal proportional to an applied magnetic field. An analog-to-digital converter converts the analog signal to a digital signal that is provided to a digital signal processing unit, which is configured to digitally track the analog output signal. The digital tracking unit comprises a delay removal circuitry configured to generate a plurality of digital signal component corresponding to a chopping phase. A non-delayed offset compensated digital output signal may be generated within the chopping phase by mathematically operating upon (e.g., adding or subtracting) the plurality of digital signal components, generated by the delay removal circuitry.
申请公布号 US9124281(B2) 申请公布日期 2015.09.01
申请号 US201414185961 申请日期 2014.02.21
申请人 Infineon Technologies AG 发明人 Motz Mario
分类号 G06F15/00;H03M1/06;G01R33/00;G01R33/07;H03M1/08;H03M1/12;H03M1/48 主分类号 G06F15/00
代理机构 Eschweiler & Associates, LLC 代理人 Eschweiler & Associates, LLC
主权项 1. A circuit, comprising: a chopping generation circuit configured to receive an analog signal and to periodically switch a polarity of the analog signal to generate a chopped signal having different polarities in temporally adjacent chopping phases; an analog-to-digital converter (ADC) configured to convert the chopped signal to a digital signal; a digital signal processing unit comprising a delay removal circuitry configured to generate a first and second digital signal components from a same chopping phase of the digital signal, and a logic element configured to add or subtract the first and second digital signal components from the same chopping phase to generate an offset compensated digital output signal; a first signal path configured to provide the digital signal from the ADC to the logic element as the first digital signal component; and a second signal path having one or more delay removal elements configured to operate upon the digital signal to generate the second digital signal component, which is provided to the logic element.
地址 Neubiberg DE