Reduction of parasitic capacitance in a semiconductor device

摘要

An apparatus is disclosed to increase a reduced a parasitic capacitance of a semiconductor device. The semiconductor device includes a modified gate region to effectively reduce an overlap capacitance and modified well regions to effectively reduce a junction capacitance. The modified gate region includes a doped region and an undoped to decrease an effective area of the overlap capacitance. The modified well regions are separated by a substantially horizontal distance to increase an effective distance of the junction capacitance. This decrease in the effective area of the overlap capacitance and this increase in the effective distance of the junction capacitance reduces the parasitic capacitance of the semiconductor device.

主权项

1. A semiconductor device, comprising:
a first region forming a source region; a second region forming a drain region; a third region forming a gate region between the source region and the drain region, the gate region having a first vertical side and a second vertical side and including a doped region and an undoped region, the doped region extending from the first vertical side of the gate region to a third vertical side and the undoped region extending from the third vertical side to the second vertical side of the gate region; a silicide region formed onto the gate region, the silicide region not contacting at least a portion of a top side of the undoped region; a first well region extending from a fourth vertical side to a fifth vertical side; a second well region extending from a sixth vertical side to a seventh vertical side, at least a portion of the fifth vertical side of the first well region contacting at least a portion of the sixth vertical side of the second well region beneath the undoped region; a first spacer formed between the first region and the gate region, the first spacer contacting at least a portion of the first vertical side of the gate region; and a second spacer formed between the second region and the gate region, the second spacer contacting at least a portion of the second vertical side of the gate region.