发明名称 Semiconductor constructions and methods of forming interconnects
摘要 Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first level. A second level of circuitry may be formed over the first dielectric region. An interconnect may be formed to extend through such second level. A second dielectric region may be formed over the second level of circuitry, and a third level of circuitry may be formed over the second dielectric region. The third level of circuitry may be electrically connected to the first level of circuitry through the interconnect. Some embodiments include constructions having interconnects extending from a first level of circuitry, through an opening in a second level of circuitry, and to a third level of circuitry; with an individual interconnect including multiple separate electrically conductive posts.
申请公布号 US9123722(B2) 申请公布日期 2015.09.01
申请号 US201414177030 申请日期 2014.02.10
申请人 Micron Technology, Inc. 发明人 Yang Ming-Chuan;Liu Zengtao T.;Sipani Vishal
分类号 H01L23/522;H01L21/768 主分类号 H01L23/522
代理机构 Wells St. John P.S. 代理人 Wells St. John P.S.
主权项 1. A semiconductor construction, comprising: a first level of circuitry; a first dielectric region over the first level of circuitry; a second level of circuitry over the first level of circuitry, the second level comprising a pattern of repeating electrically conductive features and comprising an opening through the pattern, the electrically conductive features being disposed laterally outward on both sides of the opening; a second dielectric region over the second level of circuitry; a third level of circuitry over the second dielectric region; and multiple separate electrically conductive posts extending from the third level of circuitry to the first level of circuitry through the opening.
地址 Boise ID US