发明名称 Display device
摘要 The invention provides an active matrix EL display device which can perform a clear multi-gray scale color display. In particular, the invention provides a large active matrix EL display device at low cost by a manufacturing method which can selectively form a pattern. Power supply lines in a pixel portion are arranged in matrix by the manufacturing method which can selectively form a pattern. Further, capacitance between wirings is reduced by providing a longer distance between adjacent wirings by the manufacturing method which can selectively form a pattern.
申请公布号 US9123625(B2) 申请公布日期 2015.09.01
申请号 US201414260533 申请日期 2014.04.24
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Yoshida Yasunori;Kimura Hajime;Maekawa Shinji;Nakamura Osamu;Yamazaki Shunpei
分类号 H01L27/15;H01L21/288;H01L21/768;H01L27/12;H01L27/32 主分类号 H01L27/15
代理机构 Nixon Peabody LLP 代理人 Nixon Peabody LLP ;Costellia Jeffrey L.
主权项 1. A semiconductor device comprising: a first pixel over a substrate, wherein the first pixel comprises: a semiconductor layer over the substrate;a gate electrode, wherein the semiconductor layer and the gate electrode overlap with each other;a first insulating layer between the semiconductor layer and the gate electrode;a conductive layer electrically connected to the semiconductor layer, wherein the conductive layer is one of a source wiring and a drain wiring;a first electrode electrically connected to the conductive layer;a second insulating layer over the first electrode;an electroluminescent layer over the first electrode and the second insulating layer; anda second electrode over the electroluminescent layer and the second insulating layer; a second pixel over the substrate; a third pixel over the substrate; a fourth pixel over the substrate; a first line electrically connected to the first pixel and the second pixel, a second line electrically connected to the first line; and a third line electrically connected to the third pixel and the fourth pixel and electrically connected to the second line, wherein the second line intersects with the first line and the third line, wherein the semiconductor layer comprises a portion overlapping with the gate electrode, wherein the portion overlaps with the second insulating layer, and wherein the portion does not overlap with the first electrode.
地址 Kanagawa-ken JP