Adjusting control gate overdrive of select gate transistors during programming of non-volatile memory

摘要

In a 3D stacked non-volatile memory device, multiple smaller drain-end selected gate (SGD) transistors replace one larger SGD transistor. The SGD transistors have different control gate overdrive voltages so that, during a programming operation, a discontinuous channel potential is created in an inhibited NAND string. The SGD transistor closest to the bit line has a lower control gate overdrive voltage so that the channel potential under it is lower, and the next SGD transistor has a higher control gate overdrive voltage so that the channel potential under it is higher. The different control gate overdrive voltages can be provided by programming different threshold voltages, or by providing different control gates voltages, for the SGD transistors. Undesirable reductions in a Vsgd window due to drain-induced barrier lowering can be avoided.

主权项

1. A 3D stacked non-volatile memory device, comprising:
alternating dielectric layers and conductive layers in a stack; a set of NAND strings formed in the stack, the set of NAND strings comprising one NAND string and another NAND string, the one NAND string comprising a source-end select gate transistor, a plurality of memory cells, a first drain-end select gate transistor and a second drain-end select gate transistor between the plurality of memory cells and the first drain-end select gate transistor, the another NAND string comprising a source-end select gate transistor, a plurality of memory cells, a first drain-end select gate transistor and a second drain-end select gate transistor between the a plurality of memory cells of the another NAND string and the first drain-end select gate transistor of the another NAND string, control gates of the first drain-end select gate transistors are connected to one another by one of the conductive layers, and control gates of the second drain-end select gate transistors are connected to one another by another of the conductive layers; and a control circuit in communication with the stack, the control circuit is configured to apply a program pulse to a selected memory cell of the another NAND string and, during the program pulse: to allow programming of the selected memory cell, provide the first and second drain-end select gate transistors of the another NAND string in a conductive state, and to inhibit programming in the one NAND string, provide the first and second drain-end select gate transistors of the one NAND string in a non-conductive state, while providing a control gate overdrive voltage of the first drain-end select gate transistors which is lower than a control gate overdrive voltage of the second drain-end select gate transistors, wherein for each select gate transistor of the first drain-end select gate transistors and the second drain-end select gate transistors, the control gate overdrive voltage is equal to Vgs−Vth, where Vgs is a control gate voltage minus a source voltage and Vth is a threshold voltage.