发明名称 |
NAND flash memory unit and NAND flash memory array |
摘要 |
A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an S/D region, and at least one erase transistor couple between the at least one select transistor and an S/D region. The select transistor is for selecting the string of memory cells. The erase transistor is for reducing Vt-shift of the select transistor. |
申请公布号 |
US9123418(B2) |
申请公布日期 |
2015.09.01 |
申请号 |
US201414269212 |
申请日期 |
2014.05.05 |
申请人 |
PHISON ELECTRONICS CORP. |
发明人 |
Lin Wei;Shirota Riichiro;Mitiukhina Nina;Kuo Tsai-Hao |
分类号 |
G11C16/10;G11C16/04;H01L27/115;G11C16/14 |
主分类号 |
G11C16/10 |
代理机构 |
Jianq Chyun IP Office |
代理人 |
Jianq Chyun IP Office |
主权项 |
1. A NAND flash memory unit, comprising:
a string of memory cells connected in series; two source/drain (S/D) regions coupled to two terminals of the string of memory cells; at least one select transistor coupled between a terminal of the string and an S/D region, for selecting the string of memory cells; and at least one erase transistor coupled between the at least one select transistor and the one of the two S/D regions, wherein a voltage VCG is applied to gates of the memory cells, a voltage VS/D positively higher than the voltage VCG is applied to the S/D regions, a voltage VSG satisfying an inequality of “VSG<VS/D” is applied to a gate of the at least one select transistor, and a voltage VEG satisfying the inequality of “0V≦VEG<VS/D” is applied to the gate of the at least one erase transistor. |
地址 |
Miaoli TW |