发明名称 |
Method of forming drain extended MOS transistors for high voltage circuits |
摘要 |
A device including both drain extended metal-on-semiconductor (DE_MOS) and low-voltage metal-on-semiconductor (LV_MOS) transistors and methods of manufacturing the same are provided. In one embodiment, the method includes implanting ions of a first-type at a first energy level in a drain portion of a first DE_MOS transistor in a DE_MOS region of a substrate to form the first DE_MOS transistor, and implanting ions of the first-type at a second energy level in a LV_MOS region of the substrate adjust a voltage threshold of a first LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the first DE_MOS transistor to form a drain extension of the first DE_MOS transistor. Other embodiments are also provided. |
申请公布号 |
US9123642(B1) |
申请公布日期 |
2015.09.01 |
申请号 |
US201314108967 |
申请日期 |
2013.12.17 |
申请人 |
Cypress Semiconductor Corporation |
发明人 |
Lee Sungkwon;Kouznetsov Igor;Kim Gyu-Chul |
分类号 |
H01L21/8234;H01L21/266 |
主分类号 |
H01L21/8234 |
代理机构 |
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代理人 |
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主权项 |
1. A method comprising:
implanting ions of a first-type at a first energy level in a first drain portion in a drain extended metal-on-semiconductor (DE_MOS) region of a substrate where a first DE_MOS transistor is to be formed, while concurrently implanting ions of the first-type at the first energy level in a high-voltage metal-on-semiconductor (HV_MOS) region of the substrate where a first HV MOS transistor is to be formed to adjust a threshold voltage of the first HV_MOS transistor; implanting ions of the first-type at a second energy level in a low-voltage metal-on-semiconductor (LV_MOS) region of the substrate where a first LV_MOS transistor is to be formed to adjust a threshold voltage of the first LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the first drain portion; and implanting ions of a second-type at the first energy level in a second drain portion where a second DE_MOS transistor is to be formed in the DE_MOS region while concurrently implanting ions of the second-type at the first energy level in the HV_MOS region of the substrate where a second HV_MOS transistor is to be formed to adjust the threshold voltage of the second HV_MOS transistor. |
地址 |
San Jose CA US |