发明名称 3D memory process and structures
摘要 A semiconductor device includes a substrate, a stack structure and a transistor. The substrate includes a first region and a second region. The stack structure is formed over the substrate in the first region. The transistor structure has a gate formed in the second region. A bottom portion of the gate structure is disposed at a height from the substrate that is less than a height between the substrate and a bottom portion of the stack structure.
申请公布号 US9123579(B2) 申请公布日期 2015.09.01
申请号 US201313914539 申请日期 2013.06.10
申请人 MACRONIX INTERNATIONAL CO., LTD. 发明人 Lai Erh-Kun;Chiu Chia-Jung;Lo Chieh
分类号 H01L27/115;H01L27/105 主分类号 H01L27/115
代理机构 Baker & McKenzie LLP 代理人 Baker & McKenzie LLP
主权项 1. A semiconductor device, comprising: a substrate including a memory array region and a periphery region; a stack structure of memory layers formed over the substrate in the memory array region; a transistor structure having a gate structure formed in the periphery region; an underlying layer between and adjacent to both the substrate and a bottom portion of the stack structure in the memory array region, the underlying layer solely comprising one or more non-conducting layers between the substrate and the stack structure in the memory array region; and a semiconductor layer formed on a sidewall of the stack structure and disposed in a vertical direction with respect to a major surface of the substrate, wherein the underlying layer has a thickness that is approximately equal to a height between the substrate and the bottom portion of the stack structure in the memory array region, a bottom portion of the gate structure in the periphery region is disposed at a height from the substrate that is less than the height between the substrate and the bottom portion of the stack structure in the memory array region, a first vertical surface of the semiconductor layer contacts an insulating layer formed over the gate structure, and a second vertical surface of the semiconductor layer is in contact with each of the memory layers of the stack structure.
地址 TW