Memory device, method of controlling memory device, and memory system

摘要

A memory device according to an embodiment comprises a data processing circuit that includes: a data write pre-processing circuit that processes input data to generate first intermediate data; a data write processing circuit that sequentially sets a voltage difference between a selected row line and a selected global bit line based on the first intermediate data; a data read processing circuit that detects a current flowing in the selected global bit line or a voltage of the selected global bit line and sequentially generates second intermediate data from a result of that detection; and a data read post-processing circuit that processes the second intermediate data to generate output data, the data write pre-processing circuit and the data read post-processing circuit having a correcting function that corrects a difference that may occur between the input data and the output data.

主权项

1. A memory device, comprising:
in the case that three directions intersecting each other are assumed to be an X direction, a Y direction, and a Z direction, a memory cell array including: row lines that are aligned in a two-dimensional array shape in the Y direction and the Z direction and extend in the X direction; column lines that are aligned in a two-dimensional array shape in the X direction and the Y direction and extend in the Z direction; global bit lines that are aligned in the X direction and extend in the Y direction; selection elements that are provided at ends of the column lines; and cells that are provided between the row lines and the column lines; a selection circuit including: a row line selection circuit being configured to select at least one selected row line from the row lines; a global bit line selection circuit being configured to select at least one selected global bit lines from the global bit lines; and a selection element control circuit being configured to control the selection elements to connect/disconnect between the selected global bit line and one of the column lines; and a data processing circuit including: a data write pre-processing circuit being configured to process input data to generate first intermediate data; a data write processing circuit being configured to sequentially set a voltage difference between the selected row line and the selected global bit line based on the first intermediate data; a data read processing circuit being configured to detect a current flowing in the selected global bit line or a voltage of the selected global bit line and sequentially generate second intermediate data from a result of that detection; and a data read post-processing circuit being configured to process the second intermediate data to generate output data, and the data write pre-processing circuit and the data read post-processing circuit being configured to correct a difference that may occur between the input data and the output data.