Semiconductor integrated circuit device

摘要

The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

主权项

1. A semiconductor integrated circuit device comprising:
a first column and a second column, each including a plurality of memory cells arranged along a first direction, each of the plurality of memory cells including:
a first and a second storage nodes,a first inverter, an input of which is connected to the first storage node and an output of which is connected to the second storage node, including a first p-channel transistor and a first n-channel transistor,a second inverter, an input of which is connected to the second storage node and an output of which is connected to the first storage node, including a second p-channel transistor and a second n-channel transistor,a third n-channel transistor connected to the first storage node,a fourth n-channel transistor connected to the second storage node, and a gate electrode of the fourth n-channel transistor being connected to a gate electrode of the third n-channel transistor; a plurality of word lines, each connected to gate electrodes of the third and fourth n-channel transistors of one of the plurality of memory cells included in the first column and connected to gate electrodes of the third and fourth n-channel transistors of one of the plurality of memory cells included in and the second column; a first bit line connected to the third n-channel transistors of each of the plurality of memory cells included in the first column; a second bit line connected to the fourth n-channel transistors of each of the plurality of memory cells included in the first column; a third bit line connected to the third n-channel transistor of each of the plurality of memory cells included in the second column; a fourth bit line connected to the fourth n-channel transistor of each of the plurality of memory cells included in the second column; first and second memory cell power supply lines each extending in the first direction, the first memory cell power supply line being connected to source electrodes of the first and the second p-channel transistors of each of the plurality of memory cells included in the first column, the second memory cell power supply line being connected to source electrodes of the first and the second p-channel transistors of each of the plurality of memory cells included in the second column; a power supply line that supplies a power voltage; a first transistor connected to the first memory cell power supply line and making an electrical pass between the power supply line and the first memory cell power supply line; and a second transistor connected to the second memory cell power supply line and making an electrical pass between the power supply line and the second memory cell power supply line, wherein each of the plurality of memory cells included in the first and the second column has a first p-well region, a n-well region and a second p-well region arranged along a second direction crossing with the first direction with the n-well region being arranged between the first p-well region and the second p-well region in plain view, wherein the first n-channel transistor and the fourth n-channel transistor are located in the first p-well region, wherein the first p-channel transistor and the second p-channel transistor are located in the n-well region, wherein the second n-channel transistor and the third n-channel transistor are located in the second p-well region, and wherein the first transistor is controlled according to a first column selection signal for selecting the first column and the second transistor is controlled according to a second column selection signal for selecting the second column.