Semiconductor memory apparatus including a plurality of banks and semiconductor integrated circuit including the same

摘要

A semiconductor memory apparatus includes: a memory cell area including a plurality of banks each having a plurality of octet banks corresponding to a first group and a plurality of octet banks corresponding to a second group; and a control unit configured to generate a plurality of control signals to input a data signal to any one octet bank of the first group and any one octet bank of the second group with a predetermined margin.

主权项

1. A semiconductor memory apparatus comprising:
a memory cell area comprising a plurality of banks each having a plurality of octet banks corresponding to a first group and a plurality of octet banks corresponding to a second group; and a control unit configured to generate a plurality of control signals to input a data signal to any one octet bank of the first group and any one octet bank of the second group with a first margin corresponding to first clock periods, wherein the control unit comprises: a data enable signal generator configured to generate a data enable signal having the first margin, using a command signal and an address signal; a first latch signal generator configured to generate a first latch signal to latch a data signal inputted to the octet banks of the first group, using the command signal and the address signal; a second latch signal generator configured to generate a second latch signal for latching a data signal inputted to the octet banks of the second group, using the command signal and the address signal; and an align signal generator configured to generate an align signal for aligning the data signals inputted to the octet banks of the first and second groups, using the command signal and the address signal.