Integrated circuit device, electronic device and method for detecting timing violations within a clock signal

摘要

An integrated circuit device comprises at least one clock monitor. The at least one clock monitor comprises a timer arranged to receive a clock signal, generate a first timing signal arranged to toggle between states in response to a trigger edge of the clock signal, and generate a second timing signal arranged to toggle between states in response to a trigger edge of the clock signal such that a state transition of the second timing signal in response to a trigger edge of the clock signal is delayed by a period T with respect to the trigger edge of the clock signal in response to which that transition occurs. The at least one clock monitor further comprises a detector arranged to receive at a first input thereof the first timing signal, receive at a second input thereof the second timing signal, compare states of the first and second timing signals, and configure an indication of a timing discrepancy based at least partly on the comparison of the first and second timing signals.

主权项

1. An integrated circuit device comprising at least one clock monitor, the at least one clock monitor comprising:
a timer arranged to:
receive a clock signal;generate a seed timing signal arranged to toggle between states in response to a trigger edge of the clock signal;invert the seed timing signal to generate a first timing signal; anddelay the seed timing signal by a period T to generate a second timing signal, the period T less than a period of the dock signal; and a detector arranged to:
receive at a first input thereof the first timing signal;receive at a second input thereof the second timing signal;compare states of the first and second timing signals; andgenerate an indication of a timing discrepancy signal based at least partly on the comparison of the first and second timing signals.