发明名称 |
DELAY LINE CIRCUIT WITH VARIABLE DELAY LINE UNIT |
摘要 |
A delay line circuit comprises a plurality of delay units configured to receive an input signal and modify the input signal to produce a first output signal. The delay line circuit also comprises a variable delay line unit that comprises an input end configured to receive the first output signal; an output end configured to output a second output signal; a first line between the input end and the output end, the first line comprising, in series, a first inverter, a second inverter, a first speed control unit, and a third inverter; a second line between the input end and the output end, the second line comprising, in series, a fourth inverter, a second speed control unit, a fifth inverter, and a sixth inverter. The delay line circuit is also configured to selectively transmit the received first output signal through one of the first line or the second line. |
申请公布号 |
US2015244357(A1) |
申请公布日期 |
2015.08.27 |
申请号 |
US201414187951 |
申请日期 |
2014.02.24 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
HUANG Ming-Chieh;CHERN Chan-Hong;HUANG Tsung-Ching;LIN Chih-Chang;HSUEH Fu-Lung |
分类号 |
H03K5/14 |
主分类号 |
H03K5/14 |
代理机构 |
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代理人 |
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主权项 |
1. A delay line circuit comprising:
a plurality of delay units configured to receive an input signal and modify the input signal to produce a first output signal, the plurality of delay units being configured to selectively invert or relay the input signal en route to producing the first output signal based on a first instruction received from a delay controller; and a variable delay line unit configured to receive the first output signal, the variable delay line unit comprising:
an input end configured to receive the first output signal;an output end configured to output a second output signal;a first line between the input end and the output end, the first line comprising, in series, a first inverter, a second inverter, a first speed control unit, and a third inverter; anda second line between the input end and the output end, the second line comprising, in series, a fourth inverter, a second speed control unit, a fifth inverter, and a sixth inverter, wherein the received first output signal is selectively transmitted through one of the first line or the second line based on a second instruction received from the delay line controller. |
地址 |
Hsinchu TW |