| 摘要 |
[Problem] To provide a cache memory system and a processor system with which access efficiency can be improved. [Solution] A cache memory system equipped with: a cache memory of one or more levels having a data cache unit that stores data and a tag unit that stores an address for each piece of data stored in the data cache unit; and a translation lookaside buffer (TLB) that stores page entry information, which includes address conversion information for converting from a virtual address generated by a processor to a physical address, and stores cache existence information, which indicates whether data corresponding to the respective converted physical addresses is stored in a specific cache memory of one or more levels. |
